SH7058 Datasheet, PDF (263/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Block Diagram of Channels 3 to 5: Figure 11.5 shows a block diagram of ATU-II channels 3, 4,
and 5.
STR3 to 5
Prescaler 1
TCLKA
TCLKB
TI10 (AGCK)
TI10 multiplication (AGCKM)
TIO3A
TIO3B
TIO3C
TIO3D
TIO4A
TIO4B
TIO4C
TIO4D
TIO5A
TIO5B
TIO5C
TIO5D
Clock selection
logic
(3 systems:
CH3, 4, 5)
GR3A
•••
GR3D
TCNT3
TIOR3A
TIOR3B
TCR3
GR4A
•••
GR4D
TCNT4
TIOR4A
TIOR4B
TCR4
GR5A
•••
GR5D
TCNT5
TIOR5A
TIOR5B
TCR5
TMDR
TIER3
TSR3
Compa-
rator
Control
logic
I/O control
Internal data bus and address bus
Figure 11.5 Block Diagram of Channels 3 to 5
Rev. 3.0, 09/04, page 222 of 1086
Channel 9 compare-
match trigger
Overflow interrupts × 3
Input capture/output
compare interrupts × 12