SH7058 Datasheet, PDF (626/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
10
TCR10
0
R/W Timer Clear/Set Control by CCM
Specifies whether the timer is to be cleared and
set to LOSR by the CAN-ID compare match for
receive mailboxes. When a mailbox stores a
receive message, the timer counter (TCNTR) is
automatically cleared and set to LOSR, if the
CCM bit of the corresponding mailbox and this bit
are set. CCM is not capable of generating an
interrupt signal since this is performed by the
message receive interrupt (IRR1) or remote frame
request interrupt (IRR2).
0: Timer is not cleared/set by CCM
1: Timer is cleared and set to LOSR by CCM
9
TCR9
0
R/W ICR0 Automatic Disable by CCM
Specifies whether ICR0 is to be disabled by the
CAN-ID compare match (CCM) for receive
mailboxes. When a mailbox stores a receive
message, bit 14 of this register (TCR14) is
automatically cleared and the value of ICR0 is
retained, if the CCM bit of the corresponding
mailbox and this bit are set.
0: TCR14 is not cleared by CCM
1: TCR14 is automatically cleared by CCM
8
—
0

Reserved
Writing 0 to this bit is ignored. The read value is
not guaranteed.
7
TCR7
0
R/W Drift Correction Control
Specifies whether TCNTR is to be incremented by
2 or 0 every time TCNTR reaches the cycle
specified by TDCR. If this function is not required,
TDCR must be set to H'0000.
0: Timer is incremented by 0 (i.e. retains the same
value for one clock cycle) every cycle specified
by TDCR.
1: Timer is incremented by 2 every cycle specified
by TDCR (see TDCR description).
6
—
0

Reserved
Writing 0 to this bit is ignored. The read value is
not guaranteed.
Rev. 3.0, 09/04, page 585 of 1086