SH7058 Datasheet, PDF (585/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
10
TST2
0
R/W Disable Rx Input
Controls the Rx to be supplied to the CAN Interface
block. When this bit is enabled, the Rx pin value is
supplied to the CAN interface block. When this bit is
disabled, the Rx value for the CAN block is always
retained or the Tx value internally connected if
Enable Internal Loop = 1.
0: Value of external Rx pin is supplied to the CAN
interface block
1: Enable Internal Loop = 0: Rx value is retained for
the CAN interface block
9
TST1
0
Enable Internal Loop = 1: Tx value is internally
supplied to the CAN interface block
R/W Disable Tx Output
Controls the Tx to output transmit data or retain
data. When this bit is enabled, the value of the
internal transmit output pin appears on the Tx pin.
When this bit is disabled, the Tx pin always retains
the value.
0: Value of external Tx pin is supplied from the CAN
interface block
1: Enable Internal Loop = 0: Tx value is retained
8
TST0
0
Enable Internal Loop = 1: Tx is supplied to the
internal Rx
R/W Enable Internal Loop
Enables/disables the internal Tx looped back to the
internal Rx. For details, see section 16.7.1 Test
Mode settings.
0: Rx is supplied from the Rx Pin
1: Rx is supplied from the internal Tx signal
7
MCR7
0
R/W Auto-wake Mode
Enables or disables auto-wake mode. When this bit
is set, the HCAN automatically cancels sleep mode
(MCR5) by detecting CAN bus activity (dominant
bit). When this bit is not set, the HCAN does not
automatically cancel sleep mode.
0: Auto-wake by CAN bus activity disabled
1: Auto-wake by CAN bus activity enabled
6
—
0
R
Reserved
The write value should be 0. The read value is not
guaranteed.
Rev. 3.0, 09/04, page 544 of 1086