SH7058 Datasheet, PDF (178/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Conditions set:
Address: H'00A80391
Bus cycle: CPU, data access, read, word
Interrupt requests enabled
A user break interrupt does not occur because the word access was performed on an even
address.
8.4.3 Break on DMA Cycle
1. Register settings: UBARH = H'0076
UBARL = H'BCDC
UBBR = H'00A7
UBCR = H'0000
Conditions set:
Address: H'0076BCDC
Bus cycle: DMA, data access, read, longword
Interrupt requests enabled
A user break interrupt occurs when longword data is read from address H'0076BCDC.
2. Register settings: UBARH = H'0023
UBARL = H'45C8
UBBR = H'0094
UBCR = H'0000
Conditions set:
Address: H'002345C8
Bus cycle: DMA, instruction fetch, read
(operand size not included in conditions)
Interrupt requests enabled
A user break interrupt does not occur because no instruction fetch is performed in the DMA
cycle.
Rev. 3.0, 09/04, page 137 of 1086