SH7058 Datasheet, PDF (396/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bit 6—Trigger 1B Enable (TRG1BEN): Enables or disables counter clearing for channel 1
TCNT1B. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT1B
count clock. If TCNT1B counts while clearing is enabled, TCNT1B will be cleared.
Bit 6: TRG1BEN
0
1
Description
Channel 1 counter B (TCNT1B) clearing when correction counter clear
register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value)
Channel 1 counter B (TCNT1B) clearing when correction counter clear
register (TCCLR10) = correction counter (TCNT10F) is enabled
• Bit 5—Trigger 2A Enable (TRG2AEN): Enables or disables counter clearing for channel 2
TCNT2A. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT2A
count clock. If TCNT2A counts while clearing is enabled, TCNT2A will be cleared.
Bit 5: TRG2AEN
0
1
Description
Channel 2 counter 2A (TCNT2A) clearing when correction counter clear
register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value)
Channel 2 counter 2A (TCNT2A) clearing when correction counter clear
register (TCCLR10) = correction counter (TCNT10F) is enabled
• Bit 4—Trigger 1A Enable (TRG1AEN): Enables or disables counter clearing for channel 1
TCNT1A. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT1A
count clock. If TCNT1A counts while clearing is enabled, TCNT1A will be cleared.
Bit 4: TRG1AEN
0
1
Description
Channel 1 counter 1A (TCNT1A) clearing when correction counter clear
register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value)
Channel 1 counter 1A (TCNT1A) clearing when correction counter clear
register (TCCLR10) = correction counter (TCNT10F) is enabled
• Bit 3—Trigger 0D Enable (TRG0DEN): Enables or disables channel 0 ICR0D input capture
signal requests.
Bit 3: TRG0DEN
0
1
Description
Capture requests for channel 0 input capture register (ICR0D) on event
counter (TCNT10B) compare-match are disabled
(Initial value)
Capture requests for channel 0 input capture register (ICR0D) on event
counter (TCNT10B) compare-match are enabled
Rev. 3.0, 09/04, page 355 of 1086