SH7058 Datasheet, PDF (599/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
8
IRR8
0
R
Mailbox Empty Interrupt Flag
Indicates that message transmission or
transmission cancellation has been successfully
made and this mailbox is now ready to accept a
new message data for the next transmission. This
bit is set when at least one TXPR bit is cleared.
This bit is also set by an ORed signal of the
TXACK and ABACK bits, therefore, this bit is
automatically cleared when all the TXACK and
ABACK bits are cleared. Writing 0 is ignored.
Note that this bit does not represent that all TXPR
bits are reset, whereas GSR2 does.
0: Messages set for transmission or transmission
cancellation not processed
Clearing condition: All the TXACK and ABACK
bits are cleared
1: Message has been transmitted or canceled,
and new message can be stored
Setting condition: When one of the TXPR bits is
cleared by completion of transmission or
completion of transmission cancellation, i.e.,
when a TXACK or ABACK bit is set (if MBIMR
= 0)
7
IRR7
0
R/W Overload Frame Interrupt Flag
Indicates that the HCAN has transmitted an
overload frame. It remains latched until a reset by
writing 1 to this bit. Writing 0 is ignored.
0: Clearing condition: Writing 1
1: Setting condition: Overload frame transmitted
Rev. 3.0, 09/04, page 558 of 1086