SH7058 Datasheet, PDF (181/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

8.5.6 Module Standby
After a power-on reset the UBC is in the module standby state, in which the clock supply is halted.
When using the UBC, the module standby state must be cleared before making UBC register
settings. Module standby is controlled by the System Control Register 2 (SYSCR2). See section
25.2.3, System Control Register 2 (SYSCR2), for further details.
8.5.7 Internal Clock (φ) Multiplication Ratio and UBCTRG Pulse Width
The user break controller operates in synchronization with an internal clock (φ) which is four or
eight times an input clock. Even when the same kind of clock is selected by Clock Select 1 and 0
(CKS1 and CKS0) in the user break control register (UBCR), the output pulse width of UBCTRG
is changed according to the internal clock (φ) multiplication ratio (an internal clock is eight or four
times an input clock). When the multiplication ratio is changed during the UBCTRG pulse output,
pulse width of UBCTRG is changed simultaneously.
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