SH7058 Datasheet, PDF (348/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Interval Interrupt Request Register 1 (ITVRR1)
Bit:
Initial value:
R/W:
7
ITVA9
0
R/W
6
ITVA8
0
R/W
5
ITVA7
0
R/W
4
ITVA6
0
R/W
3
ITVE9
0
R/W
2
ITVE8
0
R/W
1
ITVE7
0
R/W
0
ITVE6
0
R/W
ITVRR1 is an 8-bit readable/writable register that detects the rise of bits corresponding to the
channel 0 free-running counter (TCNT0) and controls cyclic interrupt output and A/D2 converter
activation.
ITVRR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
• Bit 7—A/D2 Converter Interval Activation Bit 9 (ITVA9): A/D2 converter activation setting
bit corresponding to bit 9 in TCNT0. The rise of bit 9 in TCNT0 is ANDed with ITVA9, and
the result is output to the A/D2 converter as an activation signal.
Bit 7: ITVA9
0
1
Description
A/D2 converter activation by rise of TCNT0 bit 9 is disabled
A/D2 converter activation by rise of TCNT0 bit 9 is enabled
(Initial value)
• Bit 6—A/D2 Converter Interval Activation Bit 8 (ITVA8): A/D2 converter activation setting
bit corresponding to bit 8 in TCNT0. The rise of bit 8 in TCNT0 is ANDed with ITVA8, and
the result is output to the A/D2 converter as an activation signal.
Bit 6: ITVA8
0
1
Description
A/D2 converter activation by rise of TCNT0 bit 8 is disabled
A/D2 converter activation by rise of TCNT0 bit 8 is enabled
(Initial value)
• Bit 5—A/D2 Converter Interval Activation Bit 7 (ITVA7): A/D2 converter activation setting
bit corresponding to bit 7 in TCNT0. The rise of bit 7 in TCNT0 is ANDed with ITVA7, and
the result is output to the A/D2 converter as an activation signal.
Bit 5: ITVA7
0
1
Description
A/D2 converter activation by rise of TCNT0 bit 7 is disabled
A/D2 converter activation by rise of TCNT0 bit 7 is enabled
(Initial value)
Rev. 3.0, 09/04, page 307 of 1086