SH7058 Datasheet, PDF (730/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

18.5.6 Usage Notes
1. When a conflict occurs between a write to ADCNT and clearing of the counter by a compare
match
When a compare match occurs during T2 state of a CPU cycle for writing to ADCNT,
ADCNT is not cleared but is written to.
However, a compare match remains effective, thus allowing a write of 1 to the interrupt status
flag and external waveform output, similar to regular compare matches.
2. When a conflict occurs between a write to ADCNT and incrementing of the counter The
counter is not incremented but is written to.
3. When a conflict occurs between clearing of the interrupt status flag and setting of the flag by
interrupt generation
When any event, such as a compare match and overflow, occurs during T2 state of a CPU
cycle for writing 0 to the interrupt status flag, the compare match takes priority thus allowing
the interrupt status flag to be set.
4. When reading the continuous scan A/D conversion data during the multi-trigger A/D
conversion is performed
Reading is performed by the DMA. Following errors are generated according to the interrupt
timing.
When reading ADDR of the first channel by the continuous scan interrupt, if MTAD is
executed on the last channel in the previous scan, the data may be overwritten again in this
scan because the first channel is converted.
18.5.7 Operation Waveform Examples
(A)
Hardware Operation
1. A compare match occurs, setting the status flag to the corresponding source.
2. Multi-trigger A/D conversion that is enabled by A/D trigger (ADTRG) in the A/D trigger
interrupt enable register (ADTIER) starts.
After Multi-trigger A/D conversion is Over
3. Multi-trigger A/D conversion result is transferred to the register that is specified by A/D select
(ADSEL) in the A/D trigger control register (ADTCR) at the start of the conversion.
4. An interrupt is generated if the multi-trigger A/D conversion end interrupt is enabled.
Rev. 3.0, 09/04, page 689 of 1086