SH7058 Datasheet, PDF (649/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.7.9 DMAC Interface
The HCAN-II can activate the DMAC when a message is received at mailbox 0 in channel 0.
When an interrupt occurs by mailbox 0 and the DMAC transfer ends after settings of the DMAC
activation has been made, the RXPR0 and RFPR0 flags are cleared automatically. An interrupt
request due to a receive interrupt from the HCAN-II cannot be sent to the CPU in this case. Figure
16.13 shows a DMAC transfer flowchart. For details on the settings of the DMAC activation, see
section 10, Direct Memory Access Controller(DMAC).
Initial setting of DMAC
Set activation source
Set source and destination addresses
Set number of transmissions and interrupts
Receive a message at
mailbox 0 in channel 0
Activate DMAC
: Processing by hardware
: Setting by user
DMAC transfer ended?
Set DMAC transfer end bit
Clear RXPR and RFPR
Enable DMAC interrupt
Interrupt to CPU
Clear DMAC interrupt flag
End
Figure 16.13 DMAC Transfer Flowchart
Rev. 3.0, 09/04, page 608 of 1086