SH7058 Datasheet, PDF (888/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit 4
FLER
0
1
Description
Flash memory operates normally
(Initial value)
Programming/erasing protection for flash memory (error protection) is invalid.
[Clearing condition] At a power-on reset or in hardware standby mode
Indicates an error occurs during programming/erasing flash memory.
Programming/erasing protection for flash memory (error protection) is valid.
[Setting condition] See section 23.6.3, Error Protection.
• Bits 3 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 0—Source Program Copy Operation (SCO): Requests the on-chip programming/erasing
program to be downloaded to the on-chip RAM.
When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically
downloaded in the on-chip RAM area specified by FTDAR.
In order to set this bit to 1, RAM emulation state must be canceled, H'A5 must be written to
FKEY, and this operation must be in the on-chip RAM.
Four NOP instructions must be executed immediately after setting this bit to 1.
For interrupts during download, see section 23.8.2, Interrupts during Programming/Erasing. For
the download time, see section 23.8.3, Other Notes.
Since this bit is cleared to 0 when download is completed, this bit cannot be read as 1.
Download by setting the SCO bit to 1 requires a special interrupt processing that performs bank
switching to the on-chip program storage area. Therefore, before issuing a download request (SCO
= 1), set VBR to H'00000000. Otherwise, the CPU gets out of control. Once download end is
confirmed, VBR can be changed to any other value.
Bit 0
SCO
0
1
Description
Download of the on-chip programming/erasing program to the on-chip RAM is not
executed
(Initial value)
[Clearing condition] When download is completed
Request that the on-chip programming/erasing program is downloaded to the on-
chip RAM is generated
[Clearing conditions] When all of the following conditions are satisfied and 1 is
written to this bit
• FKEY is written to H'A5
• During execution in the on-chip RAM
• Not in RAM emulation mode (RAMS in RAMCR = 0)
Rev. 3.0, 09/04, page 847 of 1086