SH7058 Datasheet, PDF (156/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 7.3 Interrupt Exception Processing Vectors and Priorities (cont)
Interrupt Source
WDT
ITI
HCAN1
ERS1
OVR1
RM1
SLE1
Interrupt Vector
Vector Table
Vector Address
No. Offset
Interrupt
Priority
(Initial
Value)
Corre-
sponding
IPR (Bits)
224 H'00000380 to 0 to 15 (0) IPRL
H'00000383
(7–4)
228 H'00000390 to 0 to 15 (0) IPRL
H'00000393
(3–0)
229 H'00000394 to
H'00000397
230 H'00000398 to
H'0000039B
231 H'0000039C to
H'0000039F
Priority
within IPR
Setting Default
Range Priority
High
↑1
2
3
↓4
Low
7.3 Description of Registers
7.3.1 Interrupt Priority Registers A–L (IPRA–IPRL)
Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Interrupt priority registers A–L (IPRA–IPRL) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts.
Correspondence between interrupt request sources and each of the IPRA–IPRL bits is shown in
table 7.4.
Rev. 3.0, 09/04, page 115 of 1086