SH7058 Datasheet, PDF (8/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Item
Page Revisions (See Manual for Details)
10.3.2 DMA Transfer Requests
180,
Table 10.2 Selecting On-Chip
182
Peripheral Module Request Modes with
the RS Bits
Table amended
DMAC
Transfer
Request DMAC Transfer Transfer
RS4 RS3 RS2 RS1 RS0 Source Request Signal Source
Transfer
Destination Bus Mode
0 0 0 1 1 HCAN0 RM0 (HCAN0 MB0-MB15 Don't care* Burst/cycle-
receive interrupt)
steal
MB0-MB15: HCAN0 message data
10.3.11 DMAC Access from CPU
193 Description amended
The space addressed by the DMAC is 4-cycle space.
Therefore, when the CPU becomes the bus master
and accesses the DMAC, a minimum of four internal
clock cycles (φ) are required for one bus cycle. Also,
since the DMAC is located in word space, while a
word-size access to the DMAC is completed in one
bus cycle, a longword-size access is automatically
divided into two word accesses, requiring two bus
cycles (eight basic clock cycles). These two bus
cycles are executed consecutively; a different bus
cycle is never inserted between the two word
accesses. This applies to both write accesses and
read accesses.
11.2.21 Offset Base Registers (OSBR) 341
Offset Base Registers 1 and 2 (OSBR1,
OSBR2)
Bit table amended
Dedicated input capture registers with the same input
trigger signal as that for channel 0 ICR0A
Description amended
OSBR1 and OSBR2 are 16-bit read-only registers
used exclusively for input capture. Same as the
channel 0 input capture register (ICR0A), OSBR1 and
OSBR2 use the TI0A input as their trigger signal, and
store the TCNT1A or TCNT2A value on detection of
an edge.
11.3.1 Overview
Channel 10:
(3) Multiplied clock correction block
366 Description amended
…When the 16-bit correction counter 10F (TCNT10F)
value exceeds that in 16-bit correction counter 10E
(TCNT10E) , no count-up operation is performed.
11.3.2 Free-Running Counter Operation 367
and Cyclic Counter Operation
Figure 11.13 Free-Running Counter
Operation and Overflow Timing
Figure amended
Pφ
TSTR1
STR0
TCNT0
Clock
TCNT0
00000001 00000002 00000003 00000004 00000005 00000006
TSR0
OVF0
Rev. 3.0, 09/04, page v of xxxviii