SH7058 Datasheet, PDF (614/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.5.4 Abort Acknowledge Register n (ABACK1n, ABACK0n) (n = 0, 1)
ABACK1 and ABACK0 are 16-bit readable/conditionally-writable registers. These registers
notify the host CPU that a mailbox transmission has been aborted as per its request. When an abort
has succeeded, the HCAN sets the corresponding bit in ABACK. The host CPU can clear the
ABACK bit by writing 1 to the corresponding bit. Writing 0 is ignored. An ABACK bit is used by
the HCAN to acknowledge that a TXPR bit has been cleared by the corresponding TXCR bit.
• ABACK1n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABACK1[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/
WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1
Bit
15 to 0
Bit Name
ABACK1[15:0]
Initial Value R/W
0
R/WC1
Description
Notify that the requested transmit wait
cancellation of the corresponding mailbox has
been finished successfully. Bits 15 to 0
correspond to mailboxes 31 to 16
respectively.
0: Clearing condition: Writing 1
1: Corresponding mailbox has cancelled
transmission of message
(data or remote frame)
Setting condition: Completion of transmit
wait cancellation for corresponding mailbox
Rev. 3.0, 09/04, page 573 of 1086