SH7058 Datasheet, PDF (188/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bits 15–4—Reserved: The write value should always be 0. Operation cannot be guaranteed if 1
is written to these bits.
• Bit 3—CS3 Space Size Specification (A3SZ): Specifies the CS3 space bus size. A 0 setting
specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size.
Bit 3: A3SZ
0
1
Description
Byte (8-bit) size
Word (16-bit) size
(Initial value)
• Bit 2—CS2 Space Size Specification (A2SZ): Specifies the CS2 space bus size. A 0 setting
specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size.
Bit 2: A2SZ
0
1
Description
Byte (8-bit) size
Word (16-bit) size
(Initial value)
• Bit 1—CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size. A 0 setting
specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size.
Bit 1: A1SZ
0
1
Description
Byte (8-bit) size
Word (16-bit) size
(Initial value)
• Bit 0—CS0 Space Size Specification (A0SZ): Specifies the CS0 space bus size A 0 setting
specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size.
Bit 0: A0SZ
Description
0
Byte (8-bit) size
1
Word (16-bit) size
(Initial value)
Note: A0SZ is valid only in on-chip ROM enabled mode. In on-chip ROM disabled mode, the CS0
space bus size is specified by the mode pin.
Rev. 3.0, 09/04, page 147 of 1086