SH7058 Datasheet, PDF (346/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bit 2—Compare-Match Interrupt Enable 9C (CME9C): Enables or disables interrupt requests
by CMF9C in TSR9 when CMF9C is set to 1.
Bit 2: CME9C
0
1
Description
CMI9C interrupt requested by CMF9C is disabled
CMI9C interrupt requested by CMF9C is enabled
(Initial value)
• Bit 1—Compare-Match Interrupt Enable 9B (CME9B): Enables or disables interrupt requests
by CMF9B in TSR9 when CMF9B is set to 1.
Bit 1: CME9B
0
1
Description
CMI9B interrupt requested by CMF9B is disabled
CMI9B interrupt requested by CMF9B is enabled
(Initial value)
• Bit 0—Compare-Match Interrupt Enable 9A (CME9A): Enables or disables interrupt requests
by CMF9A in TSR9 when CMF9A is set to 1.
Bit 0: CME9A
0
1
Description
CMI9A interrupt requested by CMF9A is disabled
CMI9A interrupt requested by CMF9A is enabled
(Initial value)
Timer Interrupt Enable Register 11 (TIER11)
TIER11 controls enabling/disabling of channel 11 input capture, compare-match, and overflow
interrupt requests.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
— OVE11
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
— IME11B IME11A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 3.0, 09/04, page 305 of 1086