SH7058 Datasheet, PDF (116/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 5.3 Input Frequency and Operating Frequency
PLL
Input Frequency Multiplication
Range (MHz)
Factor
Internal Clock (φ) Peripheral Clock System Clock
Frequency Range (Pφ) Frequency Frequency Range
(MHz)
Range (MHz)
(MHz)
5 to 10
×4
20 to 40
10 to 20
10 to 20
×8
40 to 80
Note: Crystal oscillator and external clock input
Two types of clock signals, internal clock (φ) and peripheral clock (Pφ) signals, are supplied and
used by the SH7058.
The internal clock signal (φ), with frequency either four or eight times the frequency of the clock
signal input from the EXTAL pin, is mainly supplied to the bus master modules such as CPU,
FPU, and DMAC.
The peripheral clock signal (Pφ), with frequency two times the frequency of the clock signal input
from the EXTAL pin, is mainly supplied to the on-chip peripheral modules. The CK pin outputs
the peripheral clock signal (Pφ) signal as the system clock signal.
Input clock (EXTAL pin)
System clock (CK pin)
Internal clock (φ)
Peripheral clock (Pφ)
Internal clock (φ) = input clock × 4 Internal clock (φ) = input clock × 8
Note: Since the input clock signal is multiplied by the PLL multiplier
circuit, the phase relationships between the input clock signal
and the other clock signals are not determined uniformly.
Figure 5.2 Frequencies and Phases of Clock Signals
5.2.2 Clock Selection
The frequency of the internal clock signal (φ) can be either four or eight times the frequency of the
input clock signal (EXTAL pin), and the frequency can be selected via the CKSEL bit in system
control register 2 (SYSCR2).
Rev. 3.0, 09/04, page 75 of 1086