SH7058 Datasheet, PDF (508/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 15.2 Registers (cont)
Channel Name
Abbreviation R/W
Initial
Value Address*²
Access
Size
3
Serial mode register 3
SMR3
R/W H'00 H'FFFFF018 8, 16
Bit rate register 3
BRR3
R/W H'FF H'FFFFF019
Serial control register 3 SCR3
R/W H'00 H'FFFFF01A
Transmit data register 3 TDR3
R/W H'FF H'FFFFF01B
Serial status register 3
SSR3
R/(W) *¹ H'84 H'FFFFF01C
Receive data register 3 RDR3
R
H'00 H'FFFFF01D
Serial direction control
register 3
SDCR3
R/W H'F2 H'FFFFF01E 8
4
Serial mode register 4
SMR4
R/W H'00 H'FFFFF020 8, 16
Bit rate register 4
BRR4
R/W H'FF H'FFFFF021
Serial control register 4 SCR4
R/W H'00 H'FFFFF022
Transmit data register 4
Serial status register 4
TDR4
SSR4
R/W H'FF
R/(W) *¹ H'84
H'FFFFF023
H'FFFFF024
Receive data register 4 RDR4
R
H'00 H'FFFFF025
Serial direction control
register 4
SDCR4
R/W H'F2 H'FFFFF026 8
Notes: Register access with an internal clock multiplication ratio of 4 requires four or five internal
clock (φ) cycles for byte access and word access, and eight or nine internal clock (φ) cycles
for longword access.
1. Only 0 can be written to clear the flags.
2. Do not access empty addresses.
Rev. 3.0, 09/04, page 467 of 1086