SH7058 Datasheet, PDF (846/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 22.2 Port A Data Register (PADR) Read/Write Operations
Bits 15 to 0:
PAIOR
Pin Function
0
General input
Other than
general input
1
General output
Other than
general output
Read
Pin state
Pin state
PADR value
PADR value
Write
Value is written to PADR, but does not affect pin
state
Value is written to PADR, but does not affect pin
state
Write value is output from pin
Value is written to PADR, but does not affect pin
state
22.2.3 Port A Port Register (PAPR)
Bit: 15
14
13
12
11
10
9
8
PA15PR PA14PR PA13PR PA12PR PA11PR PA10PR PA9PR PA8PR
Initial value: PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
PA7PR PA6PR PA5PR PA4PR PA3PR PA2PR PA1PR PA0PR
Initial value: PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
R/W: R
R
R
R
R
R
R
R
The port A port register (PAPR) is a 16-bit read-only register that always stores the value of the
port A pins. The CPU cannot write data to this register. Bits PA15PR to PA0PR correspond to
pins PA15/RxD0 to PA0/TI0A. If PAPR is read, the corresponding pin values are returned.
Rev. 3.0, 09/04, page 805 of 1086