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SH7058 Datasheet, PDF (773/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine | |||
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Pin Functions in Branch Trace Mode
Pin
AUDCK
AUDSYNC
AUDATA3 to
AUDATA0
Description
This pin outputs the peripheral module operating frequency (PÏ).
This is the clock for AUDATA synchronization.
This pin indicates whether output from AUDATA is valid.
High: Valid data is not being output
Low: An address is being output
1. When AUDSYNC is low
When a program branch or interrupt branch occurs, the AUD asserts
AUDSYNC and outputs the branch destination address. The output order is
A3âA0, A7âA4, A11âA8, A15âA12, A19âA16, A23âA20, A27âA24, A31âA28.
2. When AUDSYNC is high
When waiting for branch destination address output, these pins constantly
output 0011.
When an branch occurs, AUDATA3âAUDATA2 output 10, and AUDATA1â
AUDATA0 indicate whether a 4-, 8-, 16-, or 32-bit address is to be output by
comparing the previous fully output address with the address output this time
(see table below).
AUDATA1, AUDATA0
00 Address bits A31âA4 match; 4 address bits A3âA0 are to be
output (i.e. output is performed once).
01 Address bits A31âA8 match; 8 address bits A3âA0 and A7âA4
are to be output (i.e. output is performed twice).
10 Address bits A31âA16 match; 16 address bits A3âA0, A7âA4,
A11âA8, and A15âA12 are to be output (i.e. output is
performed four times).
11 None of the above cases applies; 32 address bits A3âA0, A7â
A4, A11âA8, and A15âA12, A19âA16, A23âA20, A27âA24,
and A31âA28 are to be output (i.e. output is performed eight
times).
Rev. 3.0, 09/04, page 732 of 1086
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