SH7058 Datasheet, PDF (738/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

19.1.3 Pin Configuration
Table 19.1 shows the H-UDI pin configuration.
Table 19.1 Pin Configuration
Pin Name
Test clock
Test mode select
Test data input
Test data output
Test reset
Abbreviation
TCK
TMS
TDI
TDO
TRST
I/O
Input
Input
Input
Output
Input
Function
Test clock input
Test mode select input signal
Serial data input
Serial data output
Test reset input signal
19.1.4 Register Configuration
Table 19.2 shows the H-UDI registers.
Table 19.2 Register Configuration
Register
Abbreviation R/W*¹ Initial Value*² Address
Access Size
(Bits)
Instruction register SDIR
R
H'E000
H'FFFFF7C0 8/16/32
Status register
SDSR
R/W
H'0B01
H'FFFFF7C2 8/16/32
Data register H
SDDRH
R/W
Undefined
H'FFFFF7C4 8/16/32
Data register L
SDDRL
R/W
Undefined
H'FFFFF7C6 8/16/32
Bypass register
SDBPR
—
—
—
—
Boundary scan
SDBSR
—
—
—
—
register
ID code register
SDIDR
—
H'001D200F —
—
Notes: 1. Indicates whether the register can be read from/written to by the CPU.
2. Initial value when the TRST signal is input. Registers are not initialized by a reset
(power-on or manual) or in standby mode.
Instructions and data can be input to the instruction register (SDIR) and data register (SDDR) by
serial transfer from the test data input pin (TDI). Data from SDIR, the status register (SDSR), and
SDDR can be output via the test data output pin (TDO). The bypass register (SDBPR) is a 1-bit
register to which TDI and TDO are connected in BYPASS, CLAMP, or HIGHZ mode. The
boundary scan register (SDBSR) is a 474-bit register, and is connected to TDI and TDO in the
SAMPLE/PRELOAD or EXTEST mode. The ID code register (SDIDR) is a 32-bit register; a
fixed code can be output via TDO in the IDCODE mode. All registers, except SDBPR, SDBSR,
and SDIDR, can be accessed from the CPU.
Rev. 3.0, 09/04, page 697 of 1086