SH7058 Datasheet, PDF (854/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

22.6 Port E
Port E is an input/output port with the 16 pins shown in figure 22.5.
Port E
ROM disabled ROM enabled
expansion mode expansion mode
A15 (output) PE15 (I/O) /A15 (output)
A14 (output) PE14 (I/O) /A14 (output)
A13 (output) PE13 (I/O) /A13 (output)
A12 (output) PE12 (I/O) /A12 (output)
A11 (output) PE11 (I/O) /A11 (output)
A10 (output) PE10 (I/O) /A10 (output)
A9 (output)
PE9 (I/O) /A9 (output)
A8 (output)
PE8 (I/O) /A8 (output)
A7 (output)
PE7 (I/O) /A7 (output)
A6 (output)
PE6 (I/O) /A6 (output)
A5 (output)
PE5 (I/O) /A5 (output)
A4 (output)
PE4 (I/O) /A4 (output)
A3 (output)
PE3 (I/O) /A3 (output)
A2 (output)
PE2 (I/O) /A2 (output)
A1 (output)
PE1 (I/O) /A1 (output)
A0 (output)
PE0 (I/O) /A0 (output)
Single-
chip mode
PE15 (I/O)
PE14 (I/O)
PE13 (I/O)
PE12 (I/O)
PE11 (I/O)
PE10 (I/O)
PE9 (I/O)
PE8 (I/O)
PE7 (I/O)
PE6 (I/O)
PE5 (I/O)
PE4 (I/O)
PE3 (I/O)
PE2 (I/O)
PE1 (I/O)
PE0 (I/O)
Figure 22.5 Port E
22.6.1 Register Configuration
The port E register configuration is shown in table 22.9.
Table 22.9 Register Configuration
Name
Abbreviation R/W Initial Value Address
Access Size
Port E data register PEDR
R/W H'0000
H'FFFFF754 8, 16
Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal
clock (φ) cycles.
Rev. 3.0, 09/04, page 813 of 1086