SH7058 Datasheet, PDF (282/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bits 2 to 0—Clock Select A2 to A0 (CKSELA2 to CKSELA0): These bits, relating to counters
DCNT8A to DCNT8H, select clock φ", scaled from the internal clock source, from φ', φ'/2,
φ'/4, φ'/8, φ'/16, and φ'/32.
Bit 2:
CKSELA2
0
1
Bit 1:
CKSELA1
0
1
0
1
Bit 0:
CKSELA0
0
1
0
1
0
1
0
1
Description
Internal clock φ": counting on φ'
Internal clock φ": counting on φ'/2
Internal clock φ": counting on φ'/4
Internal clock φ": counting on φ'/8
Internal clock φ": counting on φ'/16
Internal clock φ": counting on φ'/32
Setting prohibited
Setting prohibited
(Initial value)
Timer Control Registers 9A, 9B, 9C (TCR9A, TCR9B, TCR9C)
TCR9A
Bit:
7
6
5
4
3
2
1
0
— TRG3BEN EGSELB1 EGSELB0 — TRG3AEN EGSELA1 EGSELA0
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R/W
R/W
R/W
R
R/W
R/W
R/W
TCR9B
Bit:
Initial value:
R/W:
7
6
5
4
— TRG3DEN EGSELD1 EGSELD0
0
0
0
0
R
R/W
R/W
R/W
3
2
1
0
— TRG3CEN EGSELC1 EGSELC0
0
0
0
0
R
R/W
R/W
R/W
TCR9C
Bit:
7
—
Initial value:
0
R/W: R
6
5
4
3
— EGSELF1 EGSELF0 —
0
0
0
0
R
R/W
R/W
R
2
1
0
— EGSELE1 EGSELE0
0
0
0
R
R/W
R/W
• Bit 7—Reserved: This bit is always read as 0. The write value should always be 0.
Rev. 3.0, 09/04, page 241 of 1086