SH7058 Datasheet, PDF (187/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Number of Access Cycles for On-Chip Peripheral Module Registers
Number of Access Cycles
Module Name
Bus Width Multiplication Ratio of 4 Multiplication Ratio of 8
ROM
8
Byte: 4
Byte: 4
UBC, WDT, BSC, DMAC, 16
and INTC
Byte and word: 4, longword: 8 Byte and word: 4, longword: 8
SCI
8
Byte: 4 or 5, word: 8 or 9
Byte: 8 to 11, word: 16 to 19
ATU, APC, CMT, PFC, 16
I/O ports, H-UDI, CPG,
and power-down
Byte and word: 4 or 5,
longword: 8 or 9
Byte and word: 8 to 11,
longword: 16 to 19
AD and MTAD
8
Byte: 6 or 7, word: 12 or 13 Byte: 12 to 15, word: 24 to 27
HCAN
16
Byte and word: 6 or 7 + wait, Byte and word: 12 to 15 +
longword: 12 or 13 + wait wait, longword: 24 to 27 + wait
9.2 Description of Registers
9.2.1 Bus Control Register 1 (BCR1)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
A3SZ A2SZ A1SZ A0SZ
Initial value: 0
0
0
0
1
1
1
1
R/W: R
R
R
R
R/W R/W R/W R/W
BCR1 is a 16-bit readable/writable register that specifies the bus size of the CS spaces.
Write bits 15–0 of BCR1 during the initialization stage after a power-on reset, and do not change
the values thereafter. In on-chip ROM enabled mode, do not access any of the CS spaces until
after completion of register initialization. In on-chip ROM disabled mode, do not access any CS
space other than CS0 until after completion of register initialization.
BCR1 is initialized to H'000F by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Rev. 3.0, 09/04, page 146 of 1086