SH7058 Datasheet, PDF (327/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Each TIER is initialized to H'0000 by a power-on reset, and in hardware standby mode and
software standby mode.
Timer Interrupt Enable Register 0 (TIER0)
TIER0 controls enabling/disabling of channel 0 input capture and overflow interrupt requests.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
— OVE0 ICE0D ICE0C ICE0B ICE0A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W R/W R/W R/W R/W
• Bits 15 to 5—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 4—Overflow Interrupt Enable 0 (OVE0): Enables or disables interrupt requests by the
overflow flag (OVF0) in TSR0 when OVF0 is set to 1.
Bit 4: OVE0
0
1
Description
OVI0 interrupt requested by OVF0 is disabled
OVI0 interrupt requested by OVF0 is enabled
(Initial value)
• Bit 3—Input Capture Interrupt Enable 0D (ICE0D): Enables or disables interrupt requests by
the input capture flag (ICF0D) in TSR0 when ICF0D is set to 1. Setting the DMAC while
interrupt requests are enabled allows the DMAC to be activated by an interrupt request.
Bit 3: ICE0D
0
1
Description
ICI0D interrupt requested by ICF0D is disabled
ICI0D interrupt requested by ICF0D is enabled
(Initial value)
Rev. 3.0, 09/04, page 286 of 1086