SH7058 Datasheet, PDF (791/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bit 2—PA1 Mode Bit (PA1MD): Selects the function of pin PA1/TI0B.
Bit 2: PA1MD
0
1
Description
General input/output (PA1)
ATU-II input capture input (TI0B)
(Initial value)
• Bit 1—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 0—PA0 Mode Bit (PA0MD): Selects the function of pin PA0/TI0A.
Bit 0: PA0MD
0
1
Description
General input/output (PA0)
ATU-II input capture input (TI0A)
(Initial value)
21.3.3 Port B IO Register (PBIOR)
Bit: 15
14
13
12
11
10
9
8
PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port B IO register (PBIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 16 pins in port B. Bits PB15IOR to PB0IOR correspond to pins
PB15/PULS5/SCK2 to PB0/TO6A. PBIOR is enabled when port B pins function as general
input/output pins (PB15 to PB0) or serial clock pins (SCK0, SCK1, SCK2), and disabled
otherwise.
When port B pins function as PB15 to PB0 or SCK0, SCK1, and SCK2, a pin becomes an output
when the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0.
PBIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
Rev. 3.0, 09/04, page 750 of 1086