SH7058 Datasheet, PDF (590/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.4.3 General Status Register_n (GSR_n) (n = 0, 1)
The general status register (GSR) is a 16-bit read-only register that indicates the status of the
HCAN.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GSR GSR GSR GSR GSR GSR
543210
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
R/W:           R R R R R R
Bit
Bit Name
15 to 6 —
Initial Value R/W
0

5
GSR5
0
R
4
GSR4
0
R
Description
Reserved
The write value should be 0. The read value is not
guaranteed.
Error Passive Status
Indicates whether the CAN interface is error
passive or not. This bit is set as soon as the
HCAN enters the error passive state and is
cleared when the module enters again the error
active state. This means that this bit will remain
high during error passive and during bus off. Thus
to find out the correct state, both GSR5 and
GRS0 must be considered.
0: HCAN is not error passive
Setting condition: HCAN is in error active state
1: HCAN is error passive (if GSR0 = 0)
Setting condition: When TEC ≥ 128 or REC ≥
128
Halt/Sleep Status
Indicates whether the CAN interface is in the
halt/sleep state or not.
0: HCAN is not in the halt state nor sleep state
1: Halt mode (if MCR1 = 1) or sleep mode
(if MCR5 = 1)
Setting condition: If MCR1 is set and the CAN
bus is either in intermission or idle state
Rev. 3.0, 09/04, page 549 of 1086