SH7058 Datasheet, PDF (413/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

An example of the offset one-shot pulse output function and output cutoff function is shown in
figure 11.18.
Pφ
First prescaler 1
Second prescaler 1
Start trigger
(OSTRG1A-P)
Terminate trigger
(OSTRG0A-P)
Down-count
start trigger
(corresponding bit)
Down-counter
10A-10P clock
One-shot pulse
(TOA10-TOP10)
Down-counter
10A-10P
Synchronized with
down-counter clock
0009
0008
0007
0006
0005
0004 0003
0000
One-shot end
detection signal
One-shot end
interrupt (flag)
Figure 11.18 Offset One-Shot Pulse Output Function and Output Cutoff Function
Operation
11.3.7 Interval Timer Operation
The interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B) are connected to bits 6 to
9 and 10 to 13 of the channel 0 free-running counter (TCNT0). The ITVRR registers are 8-bit
registers; the upper 4 bits (ITVA) are used for A/D converter activation, and the lower 4 bits
(ITVE) are used for interrupt requests. ITVRR1 is connected to A/D converter 2 (AD2),
ITVRR2A to A/D converter 0 (AD0), and ITVRR2B to A/D converter 1 (AD1).
When the ITVA bit for the desired timing is set, the A/D converter is activated when the
corresponding bit of TCNT0 changes to 1.
When the ITVE bit for the desired timing is set, an interrupt can be requested when the
corresponding bit of TCNT0 changes to 1. At this time, the corresponding bit of the timer status
register (TSR0) is set. There are four interrupt sources for the respective ITVRR registers, but
there is only one interrupt vector.
To suppress interrupts and A/D converter activation, ITVRR bits should be cleared to 0.
Rev. 3.0, 09/04, page 372 of 1086