SH7058 Datasheet, PDF (417/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Pφ
STR6A
TCNT6A
Clock
TCNT6A
TSR6
UD6A
CYLR6A
Write to
BFR6A
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01
Down
Down
Down
Down
Down
Up
Up
Up
Up
Up
Data=0003
0004
Data=0004
Data=0000
BFR6A
0002
0003
0004
0000
DTR6A
TO6A
TSR6
CMF6A
*
PWM output does not change
for one cycle after activation
Cycle
0002
Cleared by
software
Cycle
0003
Cleared by
software
Cycle
Note: * Since the retained value is output, the PWM output is not guaranteed for one cycle after activation.
0004
Cleared by
software
Cycle
Duty=100%
Figure 11.22 Complementary PWM Mode Operation
0000
Cleared by
software
Cycle
Duty=0%
11.3.10 Channel 3 to 5 PWM Function
PWM mode is selected for channels 3 to 5 by setting the corresponding bits to 1 in the timer mode
register (TMDR), enabling the channels to operate as PWM timers with the same cycle.
In PWM mode, general registers D (GR3D, GR4D, GR5D) are used as cycle registers, and general
registers A to C (GR3A to GR3C, GR4A to GR4C, GR5A to GR5C) as duty registers. The
external pins (TIO3A to TIO3C, TIO4A to TIO4C, TIO5A to TIO5C) corresponding to the GRs
used as duty registers are used as PWM outputs. External pins TIO3D, TIO4D, and TIO5D should
not be used as timer outputs.
The free-running counter (TCNT) is started by making a setting in the timer start register (TSTR),
and when TCNT reaches the cycle register (GR3D, GR4D, GR5D) value, a compare-match is
generated and TCNT starts counting up again from H'0000. At the same time, the corresponding
bit is set in the timer status register (TSR) and 1 is output from the corresponding external pin.
When TCNT reaches the duty register (GR3A to GR3C, GR4A to GR4C, GR5A to GR5C) value,
0 is output to the external pin. The corresponding status flag is not set. When PWM operation is
performed by starting the free-running counter from its initial value of H'0000, PWM output is not
performed for one cycle. To perform immediate PWM output, the value in the cycle register must
be set in the free-running counter before the counter is started. If PWM operation is performed
after setting H'FFFF in the cycle register, the cycle register’s compare-match flag and overflow
flag will be set simultaneously.
Rev. 3.0, 09/04, page 376 of 1086