SH7058 Datasheet, PDF (552/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Receiving Serial Data (Synchronous Mode): Figures 15.20 and 15.21 show a sample flowchart
for receiving serial data. When switching from asynchronous mode to synchronous mode, make
sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not
be set and both transmitting and receiving will be disabled.
The procedure for receiving serial data is as follows (the steps correspond to the numbers in the
flowchart):
Initialization
1
Start of reception
Read ORER bit in SSR
ORER = 1?
No
Read RDRF bit in SSR
Yes
3
No
RDRF = 1?
Yes
Read receive data from RDR
and clear RDRF bit in SSR to 0 ⁴
No
All data received?
Yes
Clear RE bit in SCR to 0
End of reception
2
Error handling
1. SCI initialization: Set the RxD pin using the
PFC.
2. Receive error handling: If a receive error
occurs, read the ORER bit in SSR to
identify the error. After executing the
necessary error handling, clear ORER to 0.
Transmitting/receiving cannot resume if
ORER remains set to 1.
3. SCI status check and receive data read:
Read the serial status register (SSR), check
that RDRF is set to 1, then read receive
data from the receive data register (RDR)
and clear RDRF to 0. The RXI interrupt can
also be used to determine if the RDRF bit
has changed from 0 to 1.
4. Continue receiving serial data: Read RDR,
and clear RDRF to 0 before the MSB (bit 7)
of the current frame is received. If the
DMAC is started by a receive-data-full
interrupt (RXI) to read RDR, the RDRF bit is
cleared automatically so this step is
unnecessary.
Figure 15.20 Sample Flowchart for Serial Receiving (1)
Rev. 3.0, 09/04, page 511 of 1086