SH7058 Datasheet, PDF (11/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Item
Page Revisions (See Manual for Details)
11.7 Usage Notes
420 Figure amended
Figure 11.72 Contention between DCNT
Write and Underflow
Underflow signal
H'5555 is written because DCNT
write is given priority
DCNT 0001
0000
5555
12.1.4 Register Configuration
429
Table 12.2 Advanced Pulse Controller
Register
14.1.3 Register Configuration
453
Table 14.1 Register Configuration
15.1.4 Register Configuration
467
Table 15.2 Registers
Section 16 Controller Area Network-II 519-
(HCAN-II)
616
16.1.1 Features
519,
520
Interrupt status flag
(OSF)
Note amended
Note: Register access with an internal clock
multiplication ratio of 4 requires four or five internal
clock (φ) cycles.
Note amended
Notes: Register access with an internal clock
multiplication ratio of 4 requires four or five internal
clock (φ) cycles for byte access and word access, and
eight or nine internal clock (φ) cycles for longword
access.
Note amended
Notes: Register access with an internal clock
multiplication ratio of 4 requires four or five internal
clock (φ) cycles for byte access and word access, and
eight or nine internal clock (φ) cycles for longword
access.
Description amended
Register name
Before
HCAN-II_bit configuration register
Transmit wait register
Transmit wait cancel register
Receive complete register
Remote request register
After
HCAN-II_bit timing configuration register
Transmit Pending Request Register
Transmit Cancel Register
Data Frame Receive Pending Register
Remote Frame Receive Pending Register
Description amended
• Supports CAN specification 2.0A/2.0B and ISO-
11898-1
Description deleted
• Flexible interrupt structure
• Read section 16.8, Usage Notes carefully.
The following features have been added in the HCAN-
II.
• IRR0 function to notify a software reset and halt
Rev. 3.0, 09/04, page viii of xxxviii