SH7058 Datasheet, PDF (122/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

5.4.3 Related Register
Register bits relating to the oscillation stop detection function are mapped to bits 7 and 6 in the
SYSCR1 register.
Bit:
7
6
5
4
3
2
1
0
OSCSTOP INOSCE
AUDSRST RAME
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R/W
R
R
R
R
R/W
R/W
Bit 7: Crystal Oscillator Abnormal Detection (OSCSTOP)
Table 5.8 Description on OSCSTOP Bit
Bit 7
OSCSTOP
0
1
Description
Normal operation of crystal oscillator
Detection of abnormal operation of crystal oscillator and supply of clocks from
the on-chip oscillator circuit
Bit 6: Oscillation Stop Detection Function Enable (INOSEC)
Table 5.9 Description on INOSCE Bit
Bit 6
INOSCE
0
1
Description
Enables detection function of abnormal operation of the crystal oscillator.
Disables detection function of abnormal operation of the crystal oscillator.
Bits 5 to 0: See section 25, Power -Down State.
5.4.4 Precautions for Performing Oscillation Stop Detection Function
In the status where the on-chip oscillation is used due to abnormal operation of the crystal
oscillator, do not disable the oscillation stop detection function (by clearing the INOSCE bit to 0).
If the oscillation stop detection function is disabled, this LSI's operation is not guaranteed.
Rev. 3.0, 09/04, page 81 of 1086