SH7058 Datasheet, PDF (535/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Initialization
1
Start of transmission
Read TDRE bit in SSR
2
No
TDRE = 1?
Yes
Write transmit data to TDR
and clear TDRE bit in SSR to 0
All data transmitted?
3
No
Yes
Read TEND bit in SSR
No
TEND = 1?
Yes
Output break signal?
Yes
Clear port DR to 0
No
4
Clear TE bit in SCR to 0;
select theTxD pin as an
output port with the PFC
1. SCI initialization: Set the TxD pin using the
PFC. After the TE bit is set to 1, a frame of
1s is output, and transmission is enabled.
2. SCI status check and transmit data write:
Read the serial status register (SSR), check
that the TDRE bit is 1, then write transmit
data in the transmit data register (TDR) and
clear TDRE to 0.
3. Continue transmitting serial data: Read the
TDRE bit to check whether it is safe to write
(if it reads 1); if so, write data in TDR, then
clear TDRE to 0. When the DMAC is started
by a transmit-data-empty interrupt request
(TXI) in order to write data in TDR, the
TDRE bit is checked and cleared
automatically.
4. To output a break at the end of serial
transmission, first clear the port data
register (DR) to 0, then clear the TE bit to 0
in SCR and use the PFC to establish the
TxD pin as an output port.
End of transmission
Figure 15.5 Sample Flowchart for Transmitting Serial Data
Rev. 3.0, 09/04, page 494 of 1086