SH7058 Datasheet, PDF (566/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

H'800
H'802
H'804
H'806
H'808
H'80A
H'80C
Bit15
Bit0
Master control register_1 (MCR_1)
General status register_1 (GSR_1)
HCAN-II_bit timing configuration register 1_1 (HCAN-II_BCR1_1)
HCAN-II_bit timing configuration register 0_1 (HCAN-II_BCR0_1)
Interrupt register_1 (IRR_1)
Interrupt mask register_1 (IMR_1)
Transmit error
counter_1 (TEC_1)
Receive error
counter_1 (REC_1)
H'820
H'822
Transmit pending request register 1_1 (TXPR1_1)
Transmit pending request register 0_1 (TXPR0_1)
H'828
H'82A
Transmit cancel register 1_1 (TXCR1_1)
Transmit cancel register 0_1 (TXCR0_1)
H'830
H'832
Transmit acknowledge register 1_1 (TXACK1_1)
Transmit acknowledge register 0_1 (TXACK0_1)
H'838
H'83A
Abort acknowledge register 1_1 (ABACK1_1)
Abort acknowledge register 0_1 (ABACK0_1)
H'840
H'842
Data frame receive pending register 1_1 (RXPR1_1)
Data frame receive pending register 0_1 (RXPR0_1)
H'848
H'84A
Remote frame receive pending register 1_1 (RFPR1_1)
Remote frame receive pending register 0_1 (RFPR0_1)
H'850
H'852
Mailbox interrupt mask register 1_1 (MBIMR1_1)
Mailbox interrupt mask register 0_1 (MBIMR0_1)
H'858
H'85A
Unread message status register 1_1 (UMSR1_1)
Unread message status register 0_1 (UMSR0_1)
H'880
H'882
H'884
H'886
H'888
H'88A
H'88C
H'88E
H'890
H'892
H'894
H'896
H'898
H'89A
H'89C
H'89E
Timer counter register 1 (TCNTR1)
Timer control register_1 (TCR_1)
Timer status register_1 (TSR_1)
Timer drift correction register 1 (TDCR1)
Local offset register 1 (LOSR1)
CCR input capture register 1 (ICR1_cc_1)
TCNTR input capture register 1 (ICR1_tm_1)
Input capture register 1_1 (ICR1_1)
Timer compare match register 0_1 (TCMR1_1)
Timer compare match register 1_1 (TCMR1_1)
Timer compare match register 2_1 (TCMR2_1)
Cycle counter register 1 (CCR1)
Cycle maximum register 1 (CMAX1)
Timer mode register_1 (TMR_1)
Cycle counter register double buffer 1 (CCR_buf1)
Input capture register double buffer 1 (ICR0_buf1)
H'900
Mailbox 0_1 control
(StdID, ExtID, RTR, IDE, DLC, ATX, DART, MBC)
H'906
H'908
H'90A
H'90C
H'90E
H'910
Mailbox 0_1 timestamp
0
1
2
Mailbox 0_1 data
3
4
(8 bytes)
5
6
7
Mailbox 0_1 LAFM/Mailbox 0_1 TTT
H'920
H'940
H'960
Mailbox 1_1 control/timestamp/data/LAFM
Mailbox 2_1 control/timestamp/data/LAFM
Mailbox 3_1 control/timestamp/data/LAFM
H'AE0
H'AF3
H'B00
Mailbox 15_1 control/timestamp/data/LAFM
Mailbox 16_1 control/timestamp/data/LAFM
H'CA0
H'CC0
H'CE0
H'CF3
Mailbox 29_1 control/timestamp/data/LAFM
Mailbox 30_1 control/timestamp/data/LAFM
Mailbox 31_1 control/timestamp/data/LAFM
Figure 16.2 (2) HCAN-II Memory Map for Channel 1 (HCAN1)
Rev. 3.0, 09/04, page 525 of 1086