SH7058 Datasheet, PDF (869/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

22.12 Port L
Port L is an input/output port with the 14 pins shown in figure 22.11.
Port L
PL13 (I/O) /
(output)
PL12 (I/O) /
(input)
PL11 (I/O) /HRxD0 (input) /HRxD1 (input)
PL10 (I/O) /HTxD0 (output) /HTxD1 (output)
PL9 (I/O) /SCK4 (I/O) /
(input)
PL8 (I/O) /SCK3 (I/O)
PL7 (I/O) /SCK2 (I/O)
PL6 (I/O) /ADEND (output)
PL5 (I/O) /
(input)
PL4 (I/O) /
(input)
PL3 (I/O) /TCLKB (I/O)
PL2 (I/O) /TIO11B (I/O) /
(input)
PL1 (I/O) /TIO11A (I/O) /
(input)
PL0 (I/O) /TI10 (input)
Figure 22.11 Port L
22.12.1 Register Configuration
The port L register configuration is shown in table 22.21.
Table 22.21 Register Configuration
Name
Abbreviation R/W
Initial Value Address
Access Size
Port L data register PLDR
R/W
H'0000
H'FFFFF75E 8, 16
Port L port register PLPR
R
Port L pin
H'FFFFF788 8, 16
values
Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal
clock (φ) cycles.
Rev. 3.0, 09/04, page 828 of 1086