SH7058 Datasheet, PDF (75/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

2.2 Data Formats
2.2.1 Data Format in Registers
Register operands are always longwords (32 bits). When the memory operand is only a byte (8
bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure
2.6).
31
0
Longword
Figure 2.6 Data Format in Registers
2.2.2 Data Formats in Memory
Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed
from any address, but an address error will occur if an attempt is made to access word data starting
from an address other than 2n or longword data starting from an address other than 4n. In such
cases, the data accessed cannot be guaranteed. The hardware stack area, referred to by the
hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this
area holds the program counter and status register (figure 2.7).
Address 2n
Address 4n
Address m + 1 Address m + 3
Address m
Address m + 2
31
23
15
7
0
Byte Byte Byte Byte
Word
Word
Longword
Figure 2.7 Data Formats in Memory
2.2.3 Immediate Data Format
Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV,
ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data.
Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and
handled as longword data. Consequently, AND instructions with immediate data always clear the
upper 24 bits of the destination register.
Rev. 3.0, 09/04, page 34 of 1086