SH7058 Datasheet, PDF (117/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

System Control Register 2 (SYSCR2)
Bit:
7
6
5
CKSEL
–
–
Initial value:
0
0
0
R/W:
R/W
R
R
4
3
2
1
0
– MSTOP3 MSTOP2 MSTOP1 MSTOP0
0
0
0
0
1
R
R/W
R/W
R/W
R/W
System control register 2 (SYSCR2) is an 8-bit readable/writable register that selects the internal
clock signal (φ) and controls the standby state of the AUD, H-UDI, FPU, and UBC.
SYSCR2 is initialized to H’01 by a power-on reset.
Bit 7—Internal Clock (φ) Select (CKSEL): Selects the frequency of the internal clock signal (φ).
When writing to this bit, follow the procedure below.
1. Halt the DMAC and AUD (do not allow a bus cycle to be generated for the DMAC or AUD
immediately after writing to this register). However, the AUD does not need to be halted
during AUD branch trace.
2. Disable interrupts.
3. Place four NOP instructions after writing to this bit.
Bit 7: CKSEL
0
1
Description
Frequency of internal clock signal (φ) is four times the input clock frequency
(Initial value)
Frequency of internal clock signal (φ) is eight times the input clock frequency
For bits 6 to 0, see section 25, Power-Down State.
5.2.3 Notes on Register Access
The method of writing to system control register 2 (SYSCR2) is different from that of ordinary
registers to prevent inadvertent rewriting.
Be certain to use a word transfer instruction when writing data to SYSCR2. Data cannot be written
by a byte transfer instruction. As shown in figure 5.3, set the upper byte to H'3C and transfer data
using the lower byte as write data.
Data can be read by the same method as for ordinary registers.
SYSCR2 is allocated to address H'FFFFF70A. Always use a byte transfer instruction to read data.
Rev. 3.0, 09/04, page 76 of 1086