SH7058 Datasheet, PDF (655/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.8.5 Time Triggered Transmission Setting/Timer Operation Disabled
• The TTE (time trigger enable) bit for setting mailboxes must be written to 0. A failure may
occur during event triggered transmission.
• The timer must not be operated during event triggered transmission (TCR15 bit = 0). A failure
may occur during event triggered transmission.
16.8.6 Mailbox Access in HCAN Sleep Mode
Do not access a mailbox in HCAN sleep mode. When a mailbox is accessed in HCAN sleep mode,
CPU operation may be halted. CPU operation is not halted when a register is accessed in HCAN
sleep mode. Accessing a mailbox does not halt CPU operation except for in HCAN sleep mode.
Rev. 3.0, 09/04, page 614 of 1086