SH7058 Datasheet, PDF (723/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 18.4 lists the I/O port pins used for the multi-trigger A/D converter.
Table 18.4 Pin Function (MTAD)
Type
Multi-trigger A/D
Symbol
ADTO0A,
ADTO0B,
ADTO1A,
ADTO1B
Pin No.
135-138
I/O
Name
Output PWM output
Function
PWM output pins.
18.5 Operation
18.5.1 Overview
The multi-trigger A/D converter is divided into the timer parts and A/D conversion parts. The
timer parts include two channels 0 and 1, each of which includes the prescaler that can generate or
provide the selection of an input clock having the desired frequency. The following are general
descriptions of the operations of the channels and prescalers.
(1) Channels 0 and 1
Channels 0 and 1 include 16-bit free running counters (ADCNT0 and ADCNT1), 16-bit cycle
registers (ADCYLR0 and ADCYLR1), 16-bit duty registers (ADDR0A, ADDR0B, ADDR1A,
and ADDR1B), and 16-bit general registers (ADGR0A, ADGR0B, ADGR1A, and ADGR1B),
respectively. They also have external output pins of their own (ADTO0A, ADTO0B,
ADTO1A, and ADTO1B), thus allowing the channels to be used as PWM timers.
ADCNT0 and ADCNT1, which are the incrementing counters, output 0 (1)* to the external
output pins when the counter value matches the ADDR value (when ADDR ≠ ADCYLR).
When the counter value matches the ADCYLR value (when ADDR ≠ H'0000), ADCNT0 and
ADCNT1 output 1 (0)* to the external output pins, simultaneously clearing the ADCNT value
to H'0001. Due to these operations, channels 0 and 1 can output a waveform having the cycle
specified by the ADCYLR value and the duty specified by the ADDR value.
When ADDR = ADCYLR, ADCNT0 and ADCNT1 output 1 (0)* continuously to the external
output pins, thus providing a 100%-duty waveform, and when ADDR = H'0000, these counters
output 0 (1)* continuously to the external output pins, thus providing a 0%-duty waveform.
Note that the ADDR value should never be greater than the ADCYLR value.
Channels 0 and 1 also perform the compare match operation when the ADCNT value matches
the ADGR0A, ADGR0B, ADGR1A, or ADGR1B value that has been set in ADGR
previously. However, no output pins are provided. The channels can also trigger multi-trigger
A/D conversion using the compare matches. Neither ADCNT0 nor ADCNT1 is cleared when
the value matches the ADGR0A, ADGR0B, ADGR1A, or ADGR1B value.
Note: * Selected by the A/D trigger control register (ADTCR).
Rev. 3.0, 09/04, page 682 of 1086