SH7058 Datasheet, PDF (987/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit: 7
6
5
4
3
2
1
0
SSBY HIZ
—
—
—
—
—
—
Initial value: 0
0
0
1
1
1
1
1
R/W: R/W R/W
R
R
R
R
R
R
• Bit 7—Software Standby (SSBY): Specifies transition to software standby mode. The SSBY
bit cannot be set to 1 while the watchdog timer is running (when the timer enable bit (TME) in
the WDT timer control/status register (TCSR) is set to 1). To enter software standby mode,
always halt the WDT by clearing the TME bit to 0, then set the SSBY bit.
Bit 7: SSBY
0
1
Description
Executing SLEEP instruction puts the SH7058 into sleep mode (Initial value)
Executing SLEEP instruction puts the SH7058 into standby mode
• Bit 6—Port High Impedance (HIZ): In software standby mode, this bit selects whether to set
I/O port pins to high impedance or hold the pin state. The HIZ bit cannot be set to 1 when the
TME bit in the WDT timer control/status register (TCSR) is set to 1. When making the I/O
port pin state high impedance, always clear the TME bit to 0 before setting the HIZ bit.
Bit 6: HIZ
0
1
Description
Pin states held in software standby mode
Pins go to high impedance in software standby mode
(Initial value)
• Bit 5—Reserved: This bit is always read as 0. The write value should always be 0.
• Bits 4 to 0—Reserved: These bits are always read as 1. The write value should always be 1.
25.2.2 System Control Register 1 (SYSCR1)
Bit:
7
6
5
4
3
2
1
0
OSCSTOP INOSCE —
—
—
— AUDSRST RAME
Initial value: —
0
0
0
0
0
0
1
R/W:
R
R/W
R
R
R
R
R/W
R/W
System control register 1 (SYSCR1) is an 8-bit readable/writable register that performs AUD
software reset control and enables or disables access to the on-chip RAM.
SYSCR1 is initialized to H'01 by a power-on reset (at the rising edge).
• Bits 7 and 6: Refer to section 5.4, Precautions for Performing Crystal Resonator Stoppage
Detection Function.
Rev. 3.0, 09/04, page 946 of 1086