SH7058 Datasheet, PDF (708/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

two or more interrupt sources and interrupts from those sources occur simultaneously, their
priority order is the default priority order indicated at the right in table 18.2.
Table 18.2 Interrupt Exception Processing Vectors and Priorities
Interrupt Source
NMI
UBC
H-UDI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
DMAC0 DEI0
DMAC1 DEI1
DMAC2 DEI2
DMAC3 DEI3
Interrupt Vector
Vector Table
Vector Address
No. Offset
Interrupt
Priority
(Initial
Value)
Corre-
sponding
IPR (Bits)
11
H'0000002C to 16
—
H'0000002F
12
H'00000030 to 15
—
H'00000033
14
H'00000038 to 15
—
H'0000003B
64
H'00000100 to 0 to 15 (0) IPRA
H'00000103
(15–12)
65
H'00000104 to 0 to 15 (0) IPRA
H'00000107
(11–8)
66
H'00000108 to 0 to 15 (0) IPRA
H'0000010B
(7–4)
67
H'0000010C to 0 to 15 (0) IPRA
H'0000010F
(3–0)
68
H'00000110 to 0 to 15 (0) IPRB
H'00000113
(15–12)
69
H'00000114 to 0 to 15 (0) IPRB
H'00000117
(11–8)
70
H'00000118 to 0 to 15 (0) IPRB
H'0000011B
(7–4)
71
H'0000011C to 0 to 15 (0) IPRB
H'0000011F
(3–0)
72
H'00000120 to 0 to 15 (0) IPRC
H'00000123
(15–12)
74
H'00000128 to 0 to 15 (0)
H'0000012B
76
H'00000130 to 0 to 15 (0) IPRC
H'00000133
(11–8)
78
H'00000138 to 0 to 15 (0)
H'0000013B
Priority
within IPR
Setting Default
Range Priority
—
High
—
—
—
—
—
—
—
—
—
—
↑1
↓2
↑1
↓ 2 Low
Rev. 3.0, 09/04, page 667 of 1086