SH7058 Datasheet, PDF (597/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
13
IRR13
0
R/W Timer Overrun Interrupt Flag
Indicates that the timer has overrun and is reset to
the LOSR (local offset register) value. This bit is
set even when TCMR0 is enabled to clear/set the
timer value and its value is set to H'FFFF.
0: Timer has not overrun
Clearing condition: Writing 1
1: Timer has overrun
Setting condition: When the timer (TCNTR)
changes from H'FFFF to H'0000
12
IRR12
0
R/W Wake-up on Bus Activity Interrupt Flag
Indicates that a CAN bus activity is present. While
the HCAN is in sleep mode and a recessive to
dominant bit transition takes place on the CAN
bus, this bit is set. The operation of this interrupt
is set in the master control register (MCR7: Auto-
wake mode). This interrupt is cleared by writing a
1 to this bit. Writing a 0 is ignored.
0: Bus idle state
Clearing condition: Writing 1
1: CAN bus activity detected in HCAN sleep mode
Setting condition: Recessive → dominant bit
transition detection while in sleep mode
11
IRR11
0
R/W Timer Compare Match Interrupt Flag 2
Indicates that a compare-match condition
occurred to the timer compare match register 2
(TCMR2). When the value set in TCMR2 matches
the timer value (TCMR2 = TCNTR) or matches
Cycle_Count + TCNTR[15:4] depending on the
TMR2 (timer mode register) setting, this bit is set.
This bit is not set if the TCMR2 value is H'0000.
0: Timer compare match has not occurred to
TCMR2
Clearing condition: Writing 1
1: Timer compare match has occurred to TCMR2
Setting condition: TCMR2 matches the timer
value (TCMR2 = TCNTR) if TMR2 = 0 or
matches Cycle_Count + TCNTR[15:4] if TMR2
=1
Rev. 3.0, 09/04, page 556 of 1086