SH7058 Datasheet, PDF (618/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• RFPR0n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFPR0[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/
WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1
Bit
Bit Name
15 to 0 RFPR0[15:0]
Initial Value
0
R/W
R/WC1
Description
Remote request wait flags for receive
mailboxes 15 to 0.
0: Clearing condition: Writing 1
1: Corresponding mailbox has received a
remote frame
Setting condition: Completion of remote
frame reception in corresponding mailbox
16.5.7 Mailbox Interrupt Mask Register n (MBIMR1n, MBIMR0n) (n = 0, 1)
MBIMR1 and MBIMR0 are 16-bit readable/writable registers. MBIMR only masks IRR (IRR1:
data frame receive interrupt, IRR2: remote frame request interrupt, IRR8: mailbox empty
interrupt, and IRR9: message overflow interrupt) related to the mailbox activities. If a mailbox is
set for reception, the generation of a receive interrupt (IRR1, IRR2, and IRR9) is masked but the
setting of the corresponding bit in RXPR, RFPR, or UMSR is not modified. Similarly when a
mailbox is set for transmission, the generation of an interrupt signal and setting of an mailbox
empty interrupt due to successful transmission or abortion of transmission (IRR8) are masked,
however, clearing the corresponding TXPR/TXCR bit and setting the TXACK bit for successful
transmission are not masked, or clearing the corresponding TXPR/TXCR bit and setting the
ABACK bit for abortion of the transmission are not masked.
A mask is set by writing 1 to the corresponding bit for the mailbox activity to be masked. At a
reset all mailbox interrupts are masked.
Rev. 3.0, 09/04, page 577 of 1086