SH7058 Datasheet, PDF (849/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

22.3.3 Port B Port Register (PBPR)
Bit: 15
14
13
12
11
10
9
8
PB15PR PB14PR PB13PR PB12PR PB11PR PB10PR PB9PR PB8PR
Initial value: PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
PB7PR PB6PR PB5PR PB4PR PB3PR PB2PR PB1PR PB0PR
Initial value: PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
R/W: R
R
R
R
R
R
R
R
The port B port register (PBPR) is a 16-bit read-only register that always stores the value of the
port B pins. The CPU cannot write data to this register. Bits PB15PR to PB0PR correspond to
pins PB15/PULS5/SCK2 to PB0/TO6A. If PBPR is read, the corresponding pin values are
returned.
22.4 Port C
Port C is an input/output port with the five pins shown in figure 22.3.
Port C
PC4 (I/O) /
(input)
PC3 (I/O) /RxD2 (input)
PC2 (I/O) /TxD2 (output)
PC1 (I/O) /RxD1 (input)
PC0 (I/O) /TxD1 (output)
Figure 22.3 Port C
22.4.1 Register Configuration
The port C register configuration is shown in table 22.5.
Table 22.5 Register Configuration
Name
Abbreviation R/W Initial Value Address
Access Size
Port C data register PCDR
R/W H'0000
H'FFFFF73E 8, 16
Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal
clock (φ) cycles.
Rev. 3.0, 09/04, page 808 of 1086