SH7058 Datasheet, PDF (44/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 1.1 SH7058 Features (cont)
Item
Floating-point unit
(FPU)
Features
• SuperH architecture coprocessor
• Supports single-precision floating-point operations
• Supports a subset of the data types specified by the IEEE standard
• Supports invalid operation and division-by-zero exception detection
(subset of IEEE standard)
• Supports Round to Zero as the rounding mode (subset of IEEE standard)
• Sixteen 32-bit floating-point data registers
• Supports the FMAC instruction (multiply-and-accumulate instruction)
• Supports the FDIV instruction (divide instruction)
• Supports the FLDI0/FLDI1 instructions (constant 0/1 load instructions)
• Instruction delay time: Two cycles for each of FMAC, FADD, FSUB, and
FMUL instructions
• Execution pitch: One cycle for each of FMAC, FADD, FSUB, and FMUL
instructions
Clock pulse
generator
(CPG/PLL)
• On-chip clock pulse generator (maximum operating frequency: 80 MHz)
• Independent generation of CPU system clock and peripheral clock for
peripheral modules
• On-chip clock-multiplication PLL circuit (×4, ×8)
• Internal clock frequency range: 5 to 10 MHz
Interrupt controller
(INTC)
• Nine external interrupt pins (NMI, IRQ0 to IRQ7)
• 117 internal interrupt sources
(ATU-II × 75, SCI × 20, DMAC × 4, A/D × 5, WDT × 1, UBC × 1, CMT × 2,
HCAN-II × 8, H-UDI × 1)
• 16 programmable priority levels
User break
controller (UBC)
• Requests an interrupt when the CPU or DMAC generates a bus cycle
with specified conditions (interrupt can also be masked)
• Trigger pulse output (UBCTRG) on break condition
 Selection of trigger pulse width (φ ×1, ×4, ×8, ×16)
• Simplifies configuration of an on-chip debugger
Rev. 3.0, 09/04, page 3 of 1086