SH7058 Datasheet, PDF (449/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7): An example of the
setup procedure for PWM timer operation (channels 6 and 7) is shown in figure 11.60.
Start
Select counter clock 1
Set port-ATU-II connection 2
Set CYLR, BFR, DTR 3
Start count
4
1. Set the first-stage counter clock ' in prescaler register 2 and
3 (PSCR2, PSCR3), and select the second-stage counter
clock " with the CKSEL bit in the timer control register
(TCR6A, TCR6B, TCR7A, TCR7B).
2. Set the port B control register L (PBCRL) corresponding to
the waveform output port to ATU PWM output. Also set the
corresponding bit to 1 in the port B IO register (PBIOR) to
specify the output attribute.
3. Set PWM waveform output 1 output timing in the cycle
register (CYLR6A to CYLR6D, CYLR7A to CYLR7D), and
set the PWM waveform output 0 output timing in the buffer
register (BFR6A to BFR6D, BFR7A to BFR7D) and duty
register (DTR6A to DTR6D, DTR7A to DTR7D). If
necessary, an interrupt request can be sent to the CPU on a
compare-match between the CYLR value and the free-
running counter (TCNT) value by making the appropriate
setting in the interrupt enable register (TIERE). In addition,
setting the DMAC allows DMAC activation to be performed.
4. Set the corresponding bit to 1 in the timer start register
(TSTR) to start the TCNT counter for the relevant channel.
PWM waveform output
Notes: 1. Do not make a setting in DTR after the counter is
started. Use BFR to make a DTR setting.
2. 0% duty is specified by setting H'0000 in the duty
register (DTR), and 100% duty is specified by
setting buffer register (BFR) = cycle register (CYLR).
Do not set BFR > CYLR.
Figure 11.60 Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7)
Rev. 3.0, 09/04, page 408 of 1086