SH7058 Datasheet, PDF (563/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Note: Since the HCAN-II is designed based on a 16-bit bus system, longword (32-bit) access is
prohibited. Thus, word access must be used for all the registers, and word or byte access
must be used for the mailboxes.
16.2.2 Each Block Function
(1) Microprocessor Interface (MPI)
The MPI allows communication between the host CPU and the HCAN's registers/mailboxes to
control the memory interface, and the data controller, etc. It also contains the wakeup control
logic that detects the CAN bus state and notifies the MPI and the other parts of the HCAN so
that the HCAN can automatically exit sleep mode.
Contains registers such as MCR, IRR, GSR, and IMR.
(2) Mailboxes
The mailboxes are message buffers which are configured of RAM. There are 32 mailboxes,
and each mailbox stores the following information.
• CAN message control (StdID, RTR, DLC, IDE, etc.)
• CAN message data (for CAN data frames)
• Local acceptance filter mask (LAFM) during reception
• 3-bit mailbox configuration, automatic transmit bit for remote request, new message control bit
(3) Mailbox Control
The mailbox control handles the following functions.
For receive messages, compares the IDs, generates appropriate RAM addresses to store
messages from the CAN interface into the mailbox, and sets/clears corresponding registers.
To transmit messages, runs the internal arbitration to select the correct priority message which
is event-triggered, loads the message from the mailbox into the Tx-buffer of the CAN
interface, and sets/clears corresponding registers accordingly.
Arbitrates mailbox accesses between the host CPU and the CAN interface or mailbox control.
Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, and MBIMR.
(4) Timer
The timer is a block which transmits and receives messages at a specific time frame and
records the result. The timer is a 16-bit free-running up counter which is controlled by the host
CPU. It provides three 16-bit compare match registers. They can generate interrupt signals, set
or clear the counter value in the local offset value, and clear messages in the transmission
queue. Two 16-bit input capture registers are included to record timestamps on CAN messages
and synchronize the timer value globally within a CAN system.
The clock period of this timer offers a wide selection generated from the peripheral clock.
Contains registers such as TCNTR, TCR, TPSR, TDCR, LOSR, ICR0_tm, ICR0_cc,
ICR0_buf, ICR1, TCMR0, TCMR1, TCMR2, TMR, CCR, CCR_buf, and CMAX.
Important: The timer function is not supported by the SH7058.
Rev. 3.0, 09/04, page 522 of 1086