SH7058 Datasheet, PDF (742/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

19.3.2 Status Register (SDSR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
1
0
1
1
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
— SDTRF
Initial value: 0
0
0
0
0
0
0
1
R/W: R
R
R
R
R
R
R
R/W
The status register (SDSR) is a 16-bit register that can be read from and written to by the CPU.
SDSR output from TDO is possible, but serial data cannot be written to SDSR via TDI. The
SDTRF bit is output by means of a 1-bit shift. In the case of a 2-bit shift, the SDTRF bit is first
output, followed by a reserved bit.
SDSR is initialized by TRST signal input, but is not initialized by a reset or in software standby
mode.
Bits 15 to 1—Reserved: Bits 15 to 12 and 7 to 1 are always read as 0, and the write value should
always be 0. Bit 11, 9, and 8 are always read as 1, and the write value should always be 1.
Bit 0—Serial Data Transfer Control Flag (SDTRF): Indicates whether H-UDI registers can be
accessed by the CPU. The SDTRF bit is reset by the TRST signal , but is not initialized by a reset
or in software standby mode.
Bit 0: SDTRF
0
1
Description
Serial transfer to SDDR has ended, and SDDR can be accessed
Serial transfer to SDDR in progress
(Initial value)
Rev. 3.0, 09/04, page 701 of 1086