SH7058 Datasheet, PDF (558/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

15.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only)
When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting
even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit.
Note that clearing RE to 0 does not clear the receive error flags.
15.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer
rate. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it
samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse
(figure 15.24).
16 clocks
8 clocks
0
78
15 0
78
Base clock
–7.5 clocks +7.5 clocks
Receive
data (RxD)
Start bit
D0
15 0
5
D1
Synchronization
sampling timing
Data
sampling timing
Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as:
M = 0.5 – ¹ – (L – 0.5) F – ^{D – 0.5} (1 + F) • 100%
2N
N
M : Receive margin (%)
N : Ratio of clock frequency to bit rate (N = 16)
D : Clock duty cycle (D = 0 − 1.0)
L : Frame length (L = 9 − 12)
F : Absolute deviation of clock frequency
From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%:
D = 0.5, F = 0
M = (0.5 − 1/(2 • 16)) • 100%
= 46.875%
Rev. 3.0, 09/04, page 517 of 1086