SH7058 Datasheet, PDF (183/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

9.1.2 Block Diagram
Figure 9.1 shows the BSC block diagram.
On-chip
memory
control unit
Wait
control unit
RAMER
Bus interface
WCR
BCR1
–
Area
control unit
BCR2
Memory
control unit
,
BSC
WCR: Wait control register
RAMER: RAM emulation register
BCR1: Bus control register 1
BCR2: Bus control register 2
Figure 9.1 BSC Block Diagram
Rev. 3.0, 09/04, page 142 of 1086